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p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 1 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? description the lx1672 is a highly integrated power supply controller ic featuring two pwm switching regulator stages with an additional onboard linear regulator driver. the two constant frequency voltage- mode pwm phases can be easily configured as a single bi-phase high current output, two independently regulated outputs, or as a ddr memory i/o supply with a tracking ddr termination voltage supply. power loss and noise, due to the esr of the input capacitors, are minimized by operating each pwm output 180 out of phase. this architecture also minimizes capacitor requirements while maximizing regulator response. in bi-phase operation, the high current output utilizes a patented current sharing architecture, called forced current sharing ? , to allow accurate current sharing without the use of expensive current sense resistors. this patented approach also gives system designers maximum flexibility with respect to mosfet supply. each phase can utilize different supply voltages, for efficient use of available supplies, while programming the ratio of current pulled from each using one of three methods (see application section). the lx1672 incorporates fully programmable soft-start sequencing capabilities. each output can be configured to come up in any order necessary as required by the application. the lx1672 features an additional linear regulator driver output, which when coupled with an inexpensive mosfet is capable of supplying up to 5a for i/o, memory, and other supplies surrounding today?s micro-processor designs. each regulator voltage output is programmed via a simple voltage-divider network. the lx1672, utilizing mosfet rds(on) impedance, monitors maximum current limit conditions, in each pwm phase without the use of expensive current sense resistors. important: for the most current data, consult microsemi ?s website: http://www.microsemi.com ? u.s patents: 6,285,571,6,292,378 key features ? up to three independently regulated outputs ? ddr termination compliant ? bi-phase current sharing ? outputs as low as 0.8v generated from an internal 1% reference ? multiphase high current output reduces required capacitance ? integrated high current mosfet drivers ? 300khz, 500khz and 600khz high frequency operation minimizes external component requirements ? independent phase programmable soft-start and power sequencing ? adjustable linear regulator driver output ? no current-sense resistors applicati ons/benefits ? multi-output power supplies ? video card power supplies ? ddr, vddq and termination supply ? pc peripherals ? portable pc processor and i/o supply product highlight memory bus .... ddr termination memory core 12v 3.3v i/o graphics controller ddr memory lx1672 refer to typical application for complete circuit. 5v package order info pw plastic tssop 28-pin lq plastic mlpq 38-pin t a ( c) switching frequency (khz) rohs compliant / pb-free transition dc: 0518 rohs compliant / pb-free transition dc: 0512 0 to 70 300 lx1672-03cpw lx1672-03clq 0 to 70 500 lx1672-05cpw 0 to 70 600 lx1672-06clq note: available in tape & reel. append the letter s ?tr? to the part number (i.e. LX1672-06CLQ-TR) l l x x 1 1 6 6 7 7 2 2
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 2 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? absolute maximum ratings supply voltage (v cc ) dc .................................................................-0.3v to 5.5v driver supply voltage (v c x , v ccl ) dc ............................................-0.3v to 12v current sense inputs (v sx , c sx ) ....................................................... -0.3v to 12v error amplifier inputs (fb x , rf 2 , ldfb)........................................-0.3v to 5.5v input voltage (ss / enable , lddis) .................................................-0.3v to5.5v output drive peak current source (ho x , lo x )....................................1a (500ns) output drive peak current sink (ho x , lo x ) .......................................1a (500ns) operating junction temperature.................................................................. 150 c storage temperat ure range...........................................................-65 c to 150 c peak package solder reflow temp.(40 se cond max. exposure) .... 260c (+0, -5) note: exceeding these ratings could cause dama ge to the device. all voltages are with respect to ground. currents are positive into, negative out of specified terminal. x = denote phases 1 & 2 thermal data pw plastic tssop 28-pin thermal resistance - junction to a mbient , ja 85 c/w lq plastic mlpq 38-pin thermal resistance - junction to a mbient , ja 35c/w junction temperature calculation: t j = t a + (p d x jc ). the ja numbers are guidelines for the th ermal performance of the device/pc- b oard system. all of the above assume no ambient airflow. package pin out ho2 2 3 4 5 6 7 8 9 10 11 12 13 14 1 27 26 25 24 23 22 21 20 19 18 17 16 15 28 lo2 pg2 ldgd ldfb lddis dgnd agnd dis2 ss2 rf2 fb2 eo2 cs2 vc2 vc1 ho1 lo1 pg1 vccl vcc vs1 cs1 eo1 fb1 ss1 dis1 vs2 pw p ackage (top view) ho2 vc2 ldgd ldfb lddis dgnd agnd ss2 rf2 fb2 eo2 n.c. n.c. n.c. n.c. dis1 dis2 vcc vccl n.c. n.c. n.c . vc1 ho1 lo1 pg1 lo2 cs2 vs2 ss1 fb1 eo1 cs1 vs1 rsvd n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 connect bottom to power gnd pwgd n.c. (n.c. ? no internal connection n/u ? not used) rohs / pb-free 100% matte tin lead finish p p a a c c k k a a g g e e d d a a t t a a
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 3 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? functional pin description n ame d escription fb1 bi-phase operation: phase 1 and 2 voltage feedback single phase operation: phase 1 voltage feedback ? connected to the output through a resistor network to set desired output voltage of phase 1 eo x error amplifier output ? sets external compens ation for the corresponding phase denoted by ?x?. fb2 bi-phase operation: load sharing voltage sense feedback ? connec t filtered phase 2 switching output (pre- inductor) to fb 2 to ensure proper current sharing between phase 1 and phase 2. single phase operation: phase 2 voltage feedback ? connected to t he output through a resistor network (post inductor) to set desired output voltage of phase 2. rf2 bi-phase operation: load sharing voltage sense feedback reference ? sets reference for current sharing control loop. connecting filtered phase 1 switching output (pre-inductor) to ref 2 forces average current in phase 2 to be equal to phase 1. single phase operation: phase 2 voltage reference ? connected to ss2 pin as reference. vcc ic supply voltage (nominal 5v). vccl power supply pin for all low side drivers. ldfb low dropout regulator voltage feedback ? sets out put voltage of external mosfet via resistor network. cs x over-current limit set ? connecting a resistor between cs pin and the source of the high-side mosfet sets the current-limit threshold for the corresponding phase denoted by ?x?. exceeding the current-limit threshold forces the corresponding phase into hiccup mode protection. a minimum of 1k must be in series with this input. ss x soft-start/hiccup capacitor pin ? duri ng start-up, the voltage on this pin controls the output voltage of its respective regulator. an internal 20k resistor and the external capacitor set the time constant for soft-start function. the soft-start function does not initialize until the supply volta ge exceeds the uvlo threshold. when an over-current condition occurs, this capacitor is used for the timing of hiccup mode protection. agnd analog ground reference. dgnd digital ground reference. ldgd low dropout regulator gate drive ? connects to gate of external n-channel mosfet for linear regulator function. pg x driver power ground. connects to the source of t he bottom n-channel mosfets of phase 1 where x=1, and phase 2 where x=2 for the tssop. the mlpq package has a common pg output . ho x high side mosfet gate driver ? ?x? denotes corresponding phase. lo x low side mosfet gate driver ? ?x? denotes corresponding phase. vc x phase high-side mosfet gate driver supply ? connect to separate supply or boot strap supply to ensure proper high-side gate driver supply vo ltage. ?x? denotes corresponding phase. if the phase is not used connect to vcc. lddis ldo disable input. high disables the ldo output. this pin has a 100k nominal pull down resistor vs x voltage reference for current sense. this is al so the supply pin for the current sense comparator. ?x? denotes corresponding phase. this pin cannot be le ft floating, if the phase is not used connect to vcc dis x pwm disable input ? high disables the pwm output. this pin has a nominal 80k pull down resistor. ?x? denotes corresponding phase. pwgd open drain output , high at end of soft start and no fault. pulls low if any fault condition occurs. this output is present on the mlp package only. p p a a c c k k a a g g e e d d a a t t a a
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 4 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? electrical characteristics unless otherwise specified, the following specificati ons apply over the operat ing ambient temperature 0 c t a 70 c except where otherwise noted and the following test conditions: v cc = 5v, v ccl = 5v, v cx = 12v, h ox = l ox = 3000pf load. lx1672 parameter symbol test conditions min typ max units ` switching regulators input voltage v cc 4.5 5.5 v input voltage v ccl, v cx 12 v operation current i cc static and dynamic 10 ma t a = 25c 0.792 0.8 0.808 reference voltage v ss 0c < t a < 70c 0.784 0.816 v line regulation (note 2) -1 1 % load regulation (note 2) -1 1 % minimum pulse width tssop package 250 ns minimum pulse width mlpq package 150 ns maximum duty cycle lx1672-03 load = 3000pf 85 % maximum duty cycle lx1672-05 load = 3000pf 75 % maximum duty cycle lx1672-06 load = 3000pf 70 % ` error amplifiers input offset voltage vos common mode input voltage = 1v -6.0 6.0 mv dc open loop gain 70 db unity gain bandwidth ugbw 16 mhz high output voltage v oh i source = 2ma 3.5 3.8 v low output voltage v ol i sink = 10a 200 400 mv input common mode range input offset voltage < 20mv .1 3.5 v input bias current i in 0 and 3.5 v common mode input voltage 100 na ` current sense current sense bias current i set v csx = v vsx ? 0.3v , v vsx = 5v 45 50 55 a trip threshold v trip referenced to vsx , v vsx = 5v 260 300 340 mv current sense delay t csd 350 ns current sense comparator operating current i csx current into vs x pins 2 5 ma ` output drivers ? n-channel mosfets low side driver operating current i vccl static 2.5 ma high side driver operating current i vcx static 3 ma drive rise time, fall time t rf c l = 3000pf 50 ns high level output voltage v dh i source = 20ma, v ccl = 12v 10 11 v low level output voltage v dl i sink = 20ma, v ccl = 12v 0.15 0.25 v ` oscillator pwm switching frequency lx1672-03 255 300 345 khz pwm switching frequency lx1672-05 425 500 575 khz pwm switching frequency f sw lx1672-06 510 600 690 khz ramp amplitude v ramp 1.25 v pp e e l l e e c c t t r r i i c c a a l l s s
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 5 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? electrical characteristics unless otherwise specified, the following specificati ons apply over the operat ing ambient temperature 0 c t a 70 c except where otherwise noted and the following test conditions: v cc = 5v, v ccl = 5v, v cx = 12v, hox = lox = 3000pf load lx1672 parameter symbol test conditions min typ max units ` uvlo and soft-start (ss) start-up threshold (v cx ), (v ccl ) 3.5 4.0 4.5 v start-up threshold (v cc ) 4.0 4.25 4.5 v hysteresis vcc 0.1 v ss input resistance r ss 20 k ss shutdown threshold v shdn 0.15 v hiccup mode duty cycle c ss = 0.1 f 10 % ` linear regulator controller voltage reference tolerance v ldfb = 0.8v, c out = 330f 2 % source current i hdrv v out = 9v 6 ma sink current i ldrv v out = 0.4v 0.2 ma ` disable input 1.0 v pwm disable disx pull down resistance 80 ? 2.5 v ldo disable lddis pull down resistance 100 k note 1 ? x = phase 1,2 note 2 ? system specification e e l l e e c c t t r r i i c c a a l l s s
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 6 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? block diagram cs comp + - amplifier/ compensation + - error comp + - i reset r s q q v trip 20k v ref ramp oscillator uvlo l1 r 1 esr c out r 2 c in +12v +5v v out 1 r set c ss v cc lo1 ho1 vc1 cs1 fb1 ss i set pwm i set +5v eo1 vs1 vccl pg1 uvlo hiccup fault temp ss1 ss2 f r s s s 5.5v dis1 pwgd (mlp only) 16v 16v v in figure 1 ? block diagram of pwm phase 1 + - +5v +v v ref +12v ldgd ldfb lddis vc1 vout3 figure 2 ? ldo controller block diagram b b l l o o c c k k d d i i a a g g r r a a m m
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 7 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? block diagram cs comp + - amplifier/ compensation + - error comp + - i reset r s q q v trip 20k v ref hiccup ramp oscillator uvlo l2 esr c out c in +5v r set vcc lo2 ho2 vc2 cs2 fb2 ss i set pwm i set +5v eo2 vs2 vccl pg2 uvlo rf2 p hase 1 fault temp ss1 ss2 f r s s s +5v css lpf1 lpf2 5.5v 16v 16v dis 2 vin v out 2 figure 3 ? block diagram of phase 2 connected in loadshare mode note: with the mlpq package there is only one pg x output (pg1 and pg2 are common) b b l l o o c c k k d d i i a a g g r r a a m m
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 8 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? application circuit +12v l1 + +5v +5v + 1.5vdc + +3.3v l2 + +2.7v +3.3v ho2 lo2 pg2 ldgd ldfb lddis dgnd agnd dis2 ss2 rf2 fb1 eo1 cs1 vs1 vcc vccl pg1 lo1 ho1 vc1 vc2 fb2 ss1 eo2 dis1 cs2 vs2 +5v figure 4 ? bi-phase operation with phase 1 & 2 loadsharing? from 5v & 3.3v a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 9 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? application circuit +12v l1 + +5v +5v + + +5v l2 + +2.7v +3.3v 1.40vdc 2.8vdc ho2 lo2 pg2 ldgd ldfb lddis dgnd agnd dis2 ss2 rf2 fb1 eo1 cs1 vs1 vcc vccl pg1 lo1 ho1 vc1 vc2 fb2 ss1 eo2 dis1 cs2 vs2 +5v figure 5 ? bi-phase operation with phase 2 out put tracking the output of phase 1. a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 10 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? theory of operation g eneral d escription the lx1672 is a voltage-mode pulse-width modulation controller integrated circuit. the internal ramp generator frequency is fixed to 300khz. the device has external compensation, for more flexibility of output current magnitude. u nder v oltage l ockout (uvlo) at power up, the lx1672 monito rs the supply voltage for vcc, vccl, and vc x (there is no require ment for sequencing the supplies). before all supplies reach their under-voltage lock- out (uvlo) thresholds, the soft-start (ss) pin is held low to prevent soft-start from beginning, the oscillator is disabled and all mosfets are held off. there is an internal delay that will filter out transients less that 1.5sec. s oft -s tart once the supplies are above the uvlo threshold, the soft-start capacitor begins to be charged by the reference through a 20k internal resistor. the capacitor voltage at the ss pin rises as a simple rc circuit. the ss pin is connected to the error amplifier?s non-inverting input that controls the output voltage. the output voltage will follow the ss pin voltage if sufficient charging current is provided to the output capacitor. the simple rc soft-start allows the output to rise faster at the beginning and slower at the end of the soft-start interval. thus, the required charging current into the output capacitor is less at the end of the soft-start interval. a comparator monitors the ss pin voltage and indicates the e nd of soft-start when ss pin voltage reaches 95% of v ref . o ver -c urrent p rotection (ocp) and h iccup the lx1672 uses the r ds(on) of the upper mosfet, together with a resistor (r set ) to set the actual current limit point. the current sense comparator senses the mosfet current 350ns after the top mosfet is switched on in order to reduce inaccuracies due to ringing. a current source supplies a current (i set ), whose magnitude is 50a. the set resistor r set is selected to set the current limit for the application. r set and vs x should be connected directly at the upper mosfet drain and source to get an accurate measurement across the low resistance r ds(on) . when the sensed voltage across r ds(on) plus the set resistor exceeds the 300mv, v trip threshold, the ocp comparator outputs a signal to reset the pwm latch and to start hiccup mode. the soft-start capacitor (c ss ) is discharged slowly (10 times slower than when being charged up by r ss ). when the voltage on the ss pin reaches a 0.1v thre shold, hiccup finishes and the circuit soft- starts again. during hiccup bo th mosfets for that phase are held off. hiccup is disabled during the soft -start interval, allowing start up with maximum current. if the rate of rise of the output voltage is too fast, the required charging current to the output capacitor may be higher than the limit-curre nt. in this case, the peak mosfet current is regulated to the limit-current by the current- sense comparator. if the mosfet current still reaches its limit after the soft-start finishes, the hiccup is triggered again. when the output has a short circuit the hi ccup circuit ensures that the average heat generation in both mosfets and the average current is much less than in normal operation. over-current protection can also be implemented using a sense resistor, instead of using the r ds(on) of the upper mosfet, for greater set-point accuracy. o scillator f requency an internal oscillator sets the pwm switching frequency at 300khz, 500khz, or 600khz. t heory of o peration for a b i -p hase , l oad share configuration the basic principle used in loadsharing?, in a multiple phase buck converter topology, is that if multiple, identical, inductors have the same identica l voltage impressed across their leads, they must then have the same identical current passing through them. the current that we would like to balance between inductors is mainly the dc co mponent along with as much as possible the transient current. all inductors in a multiphase buck converter topology have their output side tied together at the output filter capacitors. therefore, this side of all the inductors have the same identical voltage. if the input side of the inductors can be forced to have the same equivalent dc potential on this lead, then they will have the same dc current flowing. to achieve this requirement, phase 1 will be the control phase that sets th e output operating voltage, under normal pwm operation. to force the current of phase 2 to be equal to the current of phase 1, a second feedback loop is used. phase 2 has a low pass filter connected from the input side of each inductor. this side of the inducto rs has a square wave signal that is proportional to its duty cycle. the output of each lpf is a dc (+ some ac) signal that is propo rtional to the magnitude and duty cycle of its respective inductor signal. the second feedback loop will use the output of the phase 1 lpf as a reference signal for an error amplifier that will compare this reference to the output of the phase 2 lpf. this error signal will be amplifie d and used to control the pwm circuit of phase 2. therefore, the duty cycle of phase 2 will be set so that the equivalent voltage potential will be forced across the phase 2 inductor as compared to the phase 1 inductor. this will force the current in the phase 2 inductor to follow and be equal to the current in the phase 1 inductor. there are four methods that ca n be used to implement the loadshare feature of the lx1672 in the bi-phase mode of operation. a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 11 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? theory of operation (continued) b i -p hase , l oad share ( esr m ethod ) the first method is to change the ratio of the inductors equivalent series resistance, (esr). as can be seen in the previous example, if the offset error is zero and the esr of the two inductors are identical; then th e two inductor currents will be identical. to change the ratio of current between the two inductors, the value of the inducto r?s esr can be changed to allow more current to flow through one inductor than the other. the inductor with the lower esr value will have the larger current. the inductor currents are directly proportional to the ratio of the inductor?s esr value. the following circuit description shows how to select the inductor esr for each phase where a different amount of power is taken from two different input power supplies. a typical setup will have a +5v power supply connected to the phase 1 half bridge driver and a +3.3v power supply connected to the phase 2 half bridge driver. the combined power output for this core voltage is 18w (+1.5v @ 12a). for this ex ample the +5v pow er supply will supply 7w and the +3.3v power suppl y will supply the other 11w. 7w @ 1.5v is a 4.67a current through the phase 1 inductor. 11w @ 1.5v is a 7.33a current through the phase 2 inductor. the ratio of inductor esr is inversely proportional to the power level split. 1 2 2 1 i i esr esr = the higher current inductor will have the lower esr value. if the esr of the phase 1 inductor is selected as 10m , then the esr value of the phase 2 inductor is calculated as: m ? 4 . 6 m ? 10 33 . 7 67 . 4 = ? ? ? ? ? ? a a depending on the required accuracy of this power sharing; inductors can be chosen from sta ndard vendor tables with an esr ratio close to the required values. inductors can also be designed for a given application so that there is the least amount of compromise in the inductor?s performance. 1.5v @ 12a 18w 6.4m 4.67a 7.33a 10m 1.5v + 46.7mv l1 l2 +5v @ 7w +3.3v @ 11w vout figure 7 ? ratio loadshare? using inductor esr b i -p hase , l oad share ( f eedback d ivider m ethod ) sometimes it is desirable to use th e same inductor in both phases while having a much larger current in one phase versus the other. a simple resistor divider can be used on the input side of the low pass filter that is taken off of the switching side of the inductors. if the phase 2 current is to be larger than the current in phase 1; the resistor divider is placed in the feedback path before the low pass filter that is connected to the phase 2 inductor . if the phase 2 current needs to be less than the current in phase 1; the resistor divider is then placed in the feedback path before the low pass filter that is connected to the phase 1 inductor. as in figure 7, the millivolts of dc offset created by the resistor divider network in the feedback path, appears as a voltage generator between the esr of the two inductors. a divider in the feedback path from phase 2 will cause the voltage generator to be positive at phase 2. with a divider in the feedback path of phase 1 the voltage generator becomes positive at phase 1. the phase with the positive side of the voltage generator will have the larger current. systems that operate continuously above a 30% power level can use th is method, a down side is that that the current difference betw een the two inductors still flows during a no load condition. this produces a low efficiency condition during a no load or light load state, this method should not be us ed if a wide range of output power is required. the following description and figure 8 show how to determine the value of the resistor divider network required to generate the offset voltage necessary to produce the different current ratio in the two output inductors. the power shari ng ratio is the same as that of figure 7. the offset voltage generator is symbolic for the dc voltage offset between phase 1 & 2. this voltage is generated by small changes in the duty cycle of phase 2. the output of the lpf is a dc voltage proportional to the duty cycle on its input. a small amount of attenuation by a resistor divider before the lpf of phase 2 will cause the duty cycle of phase 2 to increase to produce the added offset at v2. the high dc gain of the error amplifier will force lpf2 to always be equal to l pf1. the following calculations determine the value of the resistor divider necessary to satisfy this example. a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 12 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? theory of operation (continued) . l1, switch side l2, switch side 100 not used 62k 4700pf + - pwm input 62k 4700pf 62k tbd 100 offset voltage generator - + esr l1 10m esr l2 10m vout1 1.5v @ 12a 18w resistor divider resistor divider phase 2 error amp phase 1 phase 2 v1 v2 1.5v +73.3mv 1.5v +46.7mv 7.33a 4.67a +5v @ 7w +3.3v @ 11w lpf1 lpf2 figure 8 ? loadshare? using feedback divider offset where v1 = 1.5467 ; v2 = 1.5733 and 2 v 1 v k = then k 5.814 k 1 100 k tbd = ? = a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 13 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? theory of operation (continued) b i -p hase , l oad share? ( p roportional m ethod ) the best topology for generating a current ratio at full load and proportional between full load and no load is shown in figure 9. the dc voltage difference between lpf1 and vout is a voltage that is proportional to the current flowing in the phase 1 inductor. this voltage can be amplified and used to offset the voltage at lpf2 through a large impedance that will not signi ficantly alter the characteristics of the low pass filter. at no load there will be no offset voltage and no offset cu rrent between the two phases. this will give the highest efficiency at no load. also a speed up capacitor can be used between the offset amplifier output and the negative input of the phase 2 error amplifier. this will improve the transient response of the phase 2 output current, so that it will share more equally with phase 1 current during a transient condition. the use of a mosfet input amplif ier is required for the buffer to prevent loading the low pass filter. the gain of the offset amplifier, and the value of ra and rb, will determine the ratio of currents between the phases at full load. two external amplifiers are required or this method. l1, switch side l2, switch side 62k + - pwm input 62k 4700pf 62k offset voltage generator - + esr l1 10m esr l2 10m v ou t 1.5v @ 12 a 18 w phase 2 error amp phase 1 phase 2 v 1 v2 1.5v +73.3mv 1.5v +46.7mv 7.33a 4.67a +5v @ 7w +3.3v @ 11w lpf2 + - + - 1m 4700pf lpf1 offset amp vos rf rin ra rb rf2 fb2 figure 9 ?loadshare? using proportional control a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 14 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? theory of operation (continued) the circuit in figure 9 sums a current through a 1m resistor (rb) offsetting the phase 2 error amplifier to create an imbalance in the l1 and l2 currents. although there are many ways to calculate component valu es the approach taken here is to pick ra, rb, r in , v out , and inductor esr. a value for the remaining resistor rf can then be calculated. the first decision to be made is the current sharing ratio, follow the previous examples to understand the basics of loadshare?. the most common reason to imbalance the current in the two phases is because of limitations on the available power from the input rails for each phase. use the available input power and total required output power to determine the inductor currents for each phase. all references are to figure 9 1) calculate the voltages v1 and v2. vout esr 1 l current 1 l 1 v + = vout esr 2 l current 2 l 2 v + = 2) select values for ra and rb (ra is typically 62k ; rb is typically 1m ) 3) calculate the offset voltage vos at the output of the offset amplifier () rb ra ra 1 v 2 v 2 v vos + ? ? = ? ? ? ? ? ? 4) calculate the value for rf (select a value for r in typically 5k ) ? ? ? ? ? ? ? ? ? ? = v1 v v vos r rf out out in due to the high impedances in th is circuit layout can affect the actual current ratio by allowing some of the switching waveforms to couple into the current summing path. it may be necessary to make some adjustment in rf after the final layout is evaluated. also, the equation for rf requires very accurate numbers for the voltages to insure an accurate result. b i -p hase , l oad share? (s eries r esistor m ethod ) a fourth but less desirable way to produce the ratio current between the two phases is to add a resistor in series with one of the inductors. this will reduce the current in the inductor that has the resistor and increase the curren t in the inductor of the opposite phase. the example of figure 7 can be used to determine the current ratio by adding the value of the series resistor to the esr value of the inductor. the added resistance will lower the overall efficiency loadshare error sources with the high dc feedback gain of this second loop, all phase timing errors, r ds(on) mismatch, and voltage differences across the half bridge drivers are removed from the current sharing accuracy. the errors in the current sharing accuracy are derived from the tolerance on the inductor?s esr and the input offset voltage specification of the error amplifier. the equivalent circuit is shown next for an absolute worst case difference of phase currents between the two inductors. vout + - esr l2 esr l1 phase 2 phase 1 offset error 5mv v1 v2 figure 6 ? error amplitude nominal esr of 6m ? . esr 5% max offset error = 6mv +5% esr l1 = 6.3 m ? -5% esr l2 = 5.7 m ? 1 esrl v - 1 v a 12 current 1 phase if out = = mv 75.6 10 6.3 12 v 1 v 3 out = = ? ? mv .6 1 8 mv 6 1 v 2 v = + = a 32 14. 10 x 5.7 10 x .6 1 8 2 l esr v - 2 v current 2 phase 3 3 out = = = ? ? phase 2 current is 2.32a greater than phase 1. input bias current also contributes to imbalance. a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 15 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? application note o utput i nductor the output inductor should be selected to meet the requirements of the output voltage ripple in steady-state operation and the inductor current slew-rate during transient. the peak-to- peak output voltage ripple is: ripple ripple i esr v = where s d l v v i out in f ? = i is the inductor ripple current, l is the output inductor value and esr is the effective series resistance of the output capacitor. i should typically be in the range of 20% to 40% of the maximum output current. higher inductance results in lower output voltage ripple, allowing slightly higher esr to satisfy the transient specification. higher inductance also slows the inductor current slew rate in response to the load-current step change, i, resulting in more output-capacitor voltage droop. when using electrolytic capacitors, the cap acitor voltage droop is usually negligible, due to the large capacitance the inductor-current rise and fall times are: () out in rise v v i l t ? = and out fall v i l t = the inductance value ca n be calculated by s d i v v l out in f ? = o utput c apacitor the output capacitor is sized to meet ripple and transient performance specifications. effective series resistance (esr) is a critical parameter. when a step load current occurs, the output voltage will have a step that equals the product of the esr and the current step, i. in an advanced microprocessor power supply, the output capacitor is usually select ed for esr instead of capacitance or rms current capability. a capacitor that satisfies the esr requirements usually has a larger capacitance and current capability than strictly needed. the allowed esr can be found by: ( ) ex ripple v i i esr < + where i ripple is the inductor ripple current, i is the maximum load current step change, and v ex is the allowed output voltage excursion in the transient. electrolytic capacitors can be us ed for the output capacitor, but are less stable with age than tantalum capacitors. as they age, their esr degrades, reducing the system performance and increasing the risk of failure. it is recommended that multiple parallel capacitors be used, so that, as esr increase with age, overall performance will still meet the processor?s requirements. there is frequently strong pressu re to use the least expensive components possible; however, this could lead to degraded long- term reliability, especially in the case of filter capacitors. microsemi?s demonstration boards use the cde polymer al-el (esre) filter capacitors, which are aluminum electrolytic, and have demonstrated reliability. the os-con series from sanyo generally provides the very best performance in terms of long term esr stability and general reliability, but at a substantial cost penalty. the cde polymer al-el (esre) filter series provides excellent esr performance at a reasonable cost. beware of off- brand, very low-cost filter capa citors, which have been shown to degrade in both esr and general electrolytic characteristics over time. a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 16 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? application note (continued) i nput c apacitor the input capacitor and the input inductor, if used, are to filter the pulsating current generated by the buck converter to reduce interference to other circuits connected to the same 5v rail. in addition, the input capacitor provides local de-coupling for the buck converter. the capacitor sh ould be rated to handle the rms current requirements. the rms current is: d) d(1 i i l rms ? = where i l is the inductor current and d is the duty cycle. the maximum value occurs when d = 50%, then i rms =0.5i l . for 5v input and output in the range of 2 to 3v, the required rms current is very close to 0.5i l . s oft -s tart c apacitor the value of the soft-start capacitor determines how fast the output voltage rises and how large the inductor current is required to charge the output capacitor. the output voltage will follow the voltage at the ss pin if the re quired inductor current does not exceed the maximum allowable curre nt for the inductor. the ss pin voltage can be expressed as: ( ) ? ? = ref where r ss and c ss are the soft-start resistor and capacitor. the current required to charge the output capacitor during the soft start interval is. dt dvss cout iout = taking the derivative with respect to time results in ss ss c t/r e rsscss vrefcout iout ? = and at t=0 rsscss vrefcout ax im = the required inductor current for the output capacitor to follow the soft start voltage equals the required capacitor current plus the load current. the soft-start ca pacitor should be selected to provide the desired power on sequencing and insure that the overall inductor current does not exceed its maximum allowable rating. values of css equal to .1f or greater are unlikely to result in saturation of the output inductor unless very large output capacitors are used.. o ver -c urrent p rotection current limiting occurs at current level i cl when the voltage detected by the current sense comparator is greater than the current sense comparator threshold, v trip (300mv). trip set set ds(on) cl v r i r i = + so, a 50 r i mv 00 3 i r i v r ds(on) cl set ds(on) cl trip set ? = ? = example: for 10a current limit, us ing fds6670a mosfet (10m r ds(on) ): ? k 4 10 50 10 0.0 10 3 0. r 6 set = ? = ? note: maximum r set is 6k . any resistor 6k or greater will not allow startup since i cl will equal zero (50a x 6k = 300mv). at higher pwm frequencies or low duty cycles, where the upper gate drive is less than 350ns wide, the 350ns delay for current limit enable may result in current pulses exceeding the desired current limit set point. if the upper mosfet on time is less than 350ns and a short circuit condition occurs the duty cycle will increase, since v out will be low. the current limit circuit will be enabled when the upper gate drive exceeds 350ns although the actual peak current limit value will be higher than calculated with the above equation. short circuit protection still exis ts due to the narrow pulse width even though the magnitude of the cu rrent pulses will be higher than the calculated value. if ocp is not desired connect both vs x and vc x to vcc. do not leave them floating. a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 17 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? application note (continued) o utput d isable the lx1672 pwm mosfet driver outputs are shut off by pulling the disable (dis x ) pins above 1.2v. the ldo voltage regulator has its own disable pin (lddis) for control of this output volta ge. pulling this pin above 3v disables the ldo. p rogramming t he o utput v oltage the output voltage is sensed by the feedback pin (fb x ) which is compared to a 0.8v reference. the output voltage can be set to any voltage above 0.8v (and lower than the input voltage) by means of a resistor divider r1 - r2 (see figure 1). ) /r r (1 v v 2 1 ref out + = note: keep r 1 and r 2 close to 1k (order of magnitude) ddr v tt t ermination v oltage double data rate (ddr) sd ram requires a termination voltage (v tt ) in addition to the line driver supply voltage (vddq) and receiver supply voltage (vdd). although it is not a requirement vdd is generally e qual to vddq; so that only v tt and vddq are required.. the lx1672 can supply both voltages by using two of the three pwm phases. since the currents for v tt and (vdd plus vddq) are quite often several amps, (2a to 6a is common) a switching regulator is a logical choice v tt for ddr memory can be generated with the lx1672 by using the positive input of the pha se 2 error amplifier rf2 as a reference input from an external reference voltage v ref which is defined as one half of vddq. using v ref as the reference input will insure that all voltages are correct and track each other as specified in the jedec (eia/jesd8-9a) specification. the phase 2 output will then be equal to v ref and track the vddq supply as required. when an external reference is used the soft start will not be functional for that phase. see microsemi application note 17 for more details. a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 18 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? application note considerations 1. the power n-mosfet transistor?s total gate charge spec, (qg) should not exceed 40nc when vcx = +12v. this condition will guarantee operati on over the specified ambient temperature range. the qg value of the n-mosfet is directly related to the amount of power dissipation inside the ic package, from the two sets of mosfet drivers. the equation relating qg to the power dissipation of a mosfet driver is: pd = f * qg * vd . f = 300khs and vd is the supply voltage for the mosfet driver. the two bottom mosfet drivers are powered by the vccl pin that is connected to +5v. the upper mosfet drivers can be connected to the +12v supply or to a bootstrap supply generated by its output bridge. the bootstrap supply will be at +17v. depending on the thermal environment of the application circuit, the qg value of the n-mosfets will have to be less than the 40nc value. a typical configuration of the input voltage rails to generate the output voltages required is having the 5volt supply on phase 1 and the 3.3 volt supply on phase 2. at the max qg va lue, the two bottom mosfet drivers will dissipate 60mw each. the upper mosfet drivers for phases 1 and 2 operate off of +12volts. their dissipation is 144mw each. the total power dissipation for gate drive is 408 mw. icc x vcc =15ma x 5 v= 75mw. total package power dissipation = 483mw. us ing the thermal equation of: t j = t a + pd * oja, the junction temperature for this ic package is = 23 + .483 * 85 which = 64c. this means that the ambient temperature rise has to be less than 86c. 2. the soft-start reference input has a 300mv threshold, above which the pwm starts to operate. the internal operating reference level is set at 800mv. this means that the output voltage is 37.5% low when the pwm becomes active. this starts each phase up in the current limit mode without hiccup operation. if more than one pha se is using the 5volt rail for conversion, then their soft-sta rt capacitor values should be changed so that the two phases do not start up together. this will help reduce the amount of 5 volt input capacitance required. also the vcc pin and the vccl pin should be kept separated and should be decoup led separately. this will prevent the vcc pin from drooping back below the uvlo set point during start up. 3. if a phase is not used connect vs x and vc x pins to vcc. do not leave them floating. a floating vs x pin will result in operation resembling a hiccup condition. 4. when phases 1 and 2 are used in the bi-phase mode to current share into the same output load, the phase 2 current is forced to follow the phase 1 current. it is important to use a larger soft- start capacitor on phase 2 than phase 1 so that the phase 1 current becomes active before phase 2 becomes active. this will minimize any start up transient. it is also important to disable phase 1 and 2 at the same time . disabling phase 1 without disabling phase 2, in the bi-phase mode, allows phase 2 to turn on and off randomly because it has lost its reference. 5. the minimum r set resistor value is 1k ohm for the current limit sensing. if this resistor becomes shorted, it will do permanent damage to the ic. 6. a resistor has been put in series with the gate of the ldo pass transistor to reduce the output noi se level. the resistor value can be changed to optimize the output transient response versus output noise. 7. the ldo controller inside the ic uses the voltage at vc1 as the drive voltage. due to noise considerations ideally the voltage on the vc1 pin would be a fixed +12volt supply. when vc1 is connected to a bootstra p supply the ldo output will reflect significant switching noi se without filtering. 8. to delay the turn on of the ld o controller output, a capacitor should be connected between the lddis pin and the +5volts. the lddis input has a 100k pull down resistor, which keeps the ldo active until this pin is pulled high. during the power up sequence the capacitor connected to the lddis pin will keep the ldo off until this capacitor, being charge by the 100k pull down resistor, goes through the low input threshold level. a a p p p p l l i i c c a a t t i i o o n n
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 19 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? package dimensions pw 28-pin thin small shrink outline (tssop) c 1 2 3 p d e f a g h l b m seating plane m illimeters i nches dim min max min max a 0.85 0.95 0.033 0.037 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.003 0.008 d 9.60 9.80 0.378 0.390 e 4.30 4.50 0.169 .176 f 0.65 bsc 0.025 bsc g 0.05 0.15 0.002 0.005 h ? 1.10 ? 0.043 l 0.50 0.75 0.020 0.030 m 0 8 0 8 p 6.25 6.50 0.246 0.256 *lc ? 0.10 ? 0.004 lq 38-pin thin micro lead quad package (mlpq) g h a p d f e i b c c 1 2 3 m illimeters i nches dim min max min max a 0.20 ref 0.0078 ref b 0.18 0.30 0.007 0.011 c 0.18 0.18 0.007 0.007 d 5.00 bsc .196 bsc e 3.00 3.25 0.118 0.127 f 5.00 5.25 0.196 0.206 g 0.50 bsc 0.019 bsc h 0 0.05 0 0.19 i 0.70 0.80 0.027 0.031 p 7.00 bsc 0.275 bsc note: dimensions do not include mold flash or protrusions; these s hall not exceed 0.155mm(0.006?) on any side. lead dimension shall not include solder coverage. m m e e c c h h a a n n i i c c a a l l s s
p roduction d a ta s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 20 copyright ? 2000 rev. 1.0, 2005-08-10 www. microsemi . com lx1672 multiple output loadshare? pwm tm ? notes production data ? information contained in this document is proprietary to microsemi and is current as of publication date. this document may not be modified in any way without the express written consent of microsemi. product processing does not necessarily include testing of all parameters. microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. n n o o t t e e s s

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